PSIM
Instruction Set Reference

Contents:

Relay Logic Instructions and their Mnemonics

Use these instructions to monitor the status of bits in the data table, such as input bits and timer control word bits, and to control the state of bits in the data table, such as output bits. In the following discussion, we use an input device in our examples.

Examine if Closed (XIC)

When an input device completes its circuit the input terminal wired to the device indicates an on state. This on state is reflected in memory for the corresponding bit. When the processor finds an XIC instruction having the same address, it determines that the input device is on or closed and sets the instruction logic to true. When the input device no longer completes its circuit, the processor sets the logic for this instruction to false.

If the rung containing this instruction also contains an output instruction, the output instruction is enabled when the XIC instruction is true (input closed); a non-retentive output instruction is disabled when the XIC instruction is false (input open).

Examine if Open (XIO)

When an input device no longer completes its circuit, the input terminal wired to the device indicates an off state. This off state is reflected in memory for the corresponding bit. When the processor finds an XIO instruction having the same address, the processor determines that the input is off (input open) and sets the instruction logic to true. When the input device completes its circuit, the processor sets the logic for this instruction to false.

If the rung containing this instruction also contains an output instruction, the output instruction Is enabled when the XIO instruction is true (input open); the non retentive output instruction is disabled when the instruction is false (input closed).

Out Energize (OTE)

Use OTE instructions to set a particular bit in memory. If the address of the bit corresponds to the address of an output module terminal, the output device wired to this terminal is energized. The enabled status of this bit is determined by rung logic in your application program.

If a true logic path is established with the input instructions in the rung, the OTE instruction is enabled. If a true logic path cannot be established or rung conditions go false, the OTE instruction is disabled. When rung conditions become false, the associated output device de-energizes.

An OTE instruction is similar to a relay coil. The instruction is controlled by the preceding instructions in its programmed rung. A relay coil is controlled by contacts in its hard-wired rung. A complete logic path of true preconditions is similar to a complete electrical circuit of closed contacts.

Your program can examine a bit controlled by these instructions as often as necessary.

Output Latch and Output Unlatch (OTL), (OTU)

Output latch and output unlatch instructions are retentive output instructions. They are usually used in a pair for any data table bit they control.

When you assign an address to the OTL instruction that corresponds to the address of an output module terminal, the output device wired to this terminal is energized when the bit in memory is set (turned on or enabled). The enabled status of this bit is determined by the rung logic preceding the OTL and OTU instructions.

If a true logic path is established with the input instructions in the rung, the OTL instruction is enabled. If a true logic path is not established and the corresponding bit in memory was not previously set, the OTL instruction is not enabled. However, if a true logic path was previously established, the bit in memory is latched on and remains on, or enabled, even after the rung conditions go false.

An OTU instruction with the same address as the OTL instruction resets (disables or turns off) the bit in memory. When a true logic path is established, the OTU instruction resets its corresponding bit in memory.

Your program can examine an output controlled by OTL and OTU instructions as often as necessary.

Branching

Use branching to form parallel logic in your application program.

Your program may have two levels of parallel branches for input instructions, only a single level of output branching is permitted.

Example of nested Branching

When:

1. I:300 is true, scan continues to I:303
2. I:300 is false , scan continues to I:301
3. I:301 is true, scan continues to I:302
4. I:302 is true, scan continues to I:303
5. I:303 is true, scan continues to I:304

The processor scans rungs from left to right and from top to bottom. When the processor finds an input instruction whose logic is false, it scans the remainder of the rung as if it were false.

Input Branching

Use an input branch in your application program to permit more than one combination of input conditions to form parallel branches (OR-logic conditions). If at least one of these parallel branches forms a true logic path, the rung logic is enabled. If none of the parallel branches forms a true logic path, rung logic is not enabled, and the output instruction logic will not be true (output is not energized).

Where possible, we recommend that you place series input instructions ahead of branching instructions to reduce program scan time.

Timer and Counter Instructions and their Mnemonics:

After reading this chapter you will be familiar with the following timer and counter instructions.

Mnemonics and Description

These instructions give you many of the capabilities of timing relays or solid-state timing and counting devices.

Timer and counter instructions are output instructions that you can condition by input instructions such as examine if closed and examine if open. Timers time intervals and counters count events, as determined by your application program logic.

Each timer or counter instruction has two values associated with it. These values are:

Preset value This is your predetermined set point. You enter this value to govern the timing or counting of the instruction. When the accumulated value is equal to or greater than the preset value, a status bit is changed. You can use this bit to control an output device.

Accumulated value This is the current number of ticks that have been measured for a timer instruction; or for a counter instruction, the number of events that has occurred.

Timer and counter instructions require three words of data table, one word each for:

• accumulated value
• preset value
• control word

Data in these words is stored in integer format.

Preset and accumulated values for timers range from 0 to 9999; the values for counter preset range from 0 to 9999. Only positive timer preset values are permitted.

Timer and Counter Instructions

Timers

Control-word data for timer instructions includes:

* two timer status bits

• EN = timer enable bit
• DN = timer done bit

Timer resolution for this implementation is one second.

The timer-accumulated value shows actual time but is dependent on CRT update time. The displayed accumulated value may appear to be less than the preset when the done bit is set.

Timer On-delay (TON)

The format of a timer on-delay instruction is:

Following is a description of the operation of the TON instruction:

• The TON instruction begins to count time-base intervals when rung conditions become true. As long as rung conditions remain true, the timer increments its accumulated value (ACC) each scan until it reaches the preset value (PRE). The accumulated value is reset when rung conditions go false, regardless of whether the timer has timed out.
• The done bit (DN) is set when the accumulated value is equal to the preset value. It is reset when rung conditions become false.
• The timer enable (EN) bit is set when rung conditions are true; it is reset when rung conditions become false.

The following shows a ladder diagram program controlling an output device using the TON done bit. By substituting XIC or XIO instructions, you can turn an output on or off depending on your ladder logic.

Retentive Timer (RTO)

The entry format of a retentive timer instruction is the same as a timer on-delay instruction.

We describe the operation of the RTO instruction here.

The RTO instruction begins to count time-base intervals when rung conditions become true. As long as rung conditions remain true, the timer increments its accumulated value (ACC) each scan until it reaches the preset value (PRE). The accumulated value is retained when the Rung conditions become false.

When the rung conditions go true, timing continues from the retained accumulated value. By retaining its accumulated value, retentive timers measure the cumulative period during which rung conditions are true. You can use this instruction to turn an output on or off depending on your ladder logic.

• The accumulated value must be reset by the RES instruction. When the RES instruction having the same address as the appropriate retentive timer is enabled, the accumulated value and the control bits are reset if the RTO rung is false.
• The done bit (DN) is set when the accumulated value is equal to the preset value. However, it is not reset when rung conditions become false; it is reset only when the appropriate RES instruction is enabled.
• The enable bit (EN) is set when rung conditions are true; it is reset when rung conditions become false.

Count Up and Count Down Counters (CTU, CTD)

The formats of the CTD and CTU instructions are:

Count up and count down instructions count false-true rung transitions. These rung transitions could be caused by events occurring in the program such as parts traveling past a detector or actuating a limit switch.

Each count is retained when the rung conditions again become false. The count is retained until an RES instruction having the same address as the counter instruction is enabled.

Each counter instruction has a preset and accumulated value and a control word associated with it.

The control word for counter instructions includes two status bits.

• CU, CD, CZ = counter enable bits
• DN = counter done bit, accumulated value is greater than or equal to preset value.

When rung conditions for a CTU instruction have a false-to-true transition, the accumulated value is incremented by one count. When this occurs successively so that the accumulated value becomes equal to the preset value, the counter done (DN) bit is set and remains set if it exceeds the preset.

CTU instructions can count beyond their preset value. When counting continues past the preset value and reaches (9999 + 1), the accumulator resets to zero.

CTD instructions also count false-to-true rung transitions. The counter-accumulated value is decrement one count for each false-to-true transition. When a sufficient number of counts has occurred and the accumulated value becomes less than the preset value, the counter done bit is reset.

When a CTD instruction counts beyond its preset value and reaches (-9999 - 1), the accumulator resets to zero.

CTU and CTD instructions are retentive. The accumulated value is retained after the CTU or CTD instruction goes false.

Reset (RES)

This output instruction has the format -(RES)-. You use a reset instruction to reset timing and counting instructions. When the RES instruction is enabled, it resets the timer, count up, or count down instruction having the same address as the RES instruction.

When an RES instruction is enabled, it resets the following:

• *timer:

• accumulated value
• done bit
• timing bit
• enable bit

• count up and count down counter :

• accumulated value
• counter done bit
• counter enable bits
• If the counter rung is enabled, the CU or CD bit will be reset as long as the RES instruction is enabled.
• CZ is set if counter = 0

If your preset value is negative, the RES instruction sets the accumulated value to zero. This, in turn, causes the done bit to be set by the count down or count up instruction.

Comparison Instructions.

The comparison instructions let you compare a value contained in a data table word against a fixed value, also known as an immediate value. These instructions are classified as input instructions. The comparisons that may be performed are:

The parameters are in one case a logical address and in the other case a program constant. A brief description for each instruction follows.

Equal (EQU)

The format of the Equal instruction is:

When the Value of the number contained within the logical address specified is equal to the program constant then this instruction becomes logically true. If the values are not equal then the instruction becomes logically false. In this case the word at address I:1 is not equal to 2, therefore the instruction is false.

Not Equal (NEQ)

The format of the Not Equal instruction is:

When the Value of the number contained within the logical address specified is not equal to the program constant then this instruction becomes logically true. If the values are equal then the instruction becomes logically false. In this case the word at address I:1 is not equal to 2, therefore the instruction is true.

Less Than (LES)

The format of the Less Than instruction is:

When the Value of the number contained within the logical address specified is less than the program constant then this instruction becomes logically true. If the value is greater than or equal then the instruction becomes logically false. In this case the value at address I:1 is less than 2, therefore the instruction is true.

Less Than or Equal (LEQ)

The format of the Less Than or Equal instruction is:

When the Value of the number contained within the logical address specified is less than or equal to the program constant then this instruction becomes logically true. If the value is greater then the instruction becomes logically false. In this case the value at address I:1 is less than or equal to 2, therefore the instruction is true.

Greater Than (GRT)

The format of the Greater Than instruction is:

When the Value of the number contained within the logical address specified is greater Than the program constant then this instruction becomes logically true. If the value is Less than or equal to then the instruction becomes logically false. In this case the value at address I:1 is not greater than 2, therefore the instruction is false.

Greater Than or Equal (GEQ)

The format of the Greater Than or Equal instruction is:

When the Value of the number contained within the logical address specified is Greater Than or Equal to the program constant then this instruction becomes logically true. If the value is less than then the instruction becomes logically false. In this case the value contained at address I:1 is not greater than or equal to 2, therefore the value of the instruction is false.